
alignment-doublelist:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400570 <_init>:
  400570:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400574:	910003fd 	mov	x29, sp
  400578:	94000040 	bl	400678 <call_weak_fn>
  40057c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400580:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400590 <.plt>:
  400590:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400594:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf2b4>
  400598:	f947fe11 	ldr	x17, [x16, #4088]
  40059c:	913fe210 	add	x16, x16, #0xff8
  4005a0:	d61f0220 	br	x17
  4005a4:	d503201f 	nop
  4005a8:	d503201f 	nop
  4005ac:	d503201f 	nop

00000000004005b0 <exit@plt>:
  4005b0:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  4005b4:	f9400211 	ldr	x17, [x16]
  4005b8:	91000210 	add	x16, x16, #0x0
  4005bc:	d61f0220 	br	x17

00000000004005c0 <malloc@plt>:
  4005c0:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  4005c4:	f9400611 	ldr	x17, [x16, #8]
  4005c8:	91002210 	add	x16, x16, #0x8
  4005cc:	d61f0220 	br	x17

00000000004005d0 <__libc_start_main@plt>:
  4005d0:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  4005d4:	f9400a11 	ldr	x17, [x16, #16]
  4005d8:	91004210 	add	x16, x16, #0x10
  4005dc:	d61f0220 	br	x17

00000000004005e0 <__gmon_start__@plt>:
  4005e0:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  4005e4:	f9400e11 	ldr	x17, [x16, #24]
  4005e8:	91006210 	add	x16, x16, #0x18
  4005ec:	d61f0220 	br	x17

00000000004005f0 <abort@plt>:
  4005f0:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  4005f4:	f9401211 	ldr	x17, [x16, #32]
  4005f8:	91008210 	add	x16, x16, #0x20
  4005fc:	d61f0220 	br	x17

0000000000400600 <puts@plt>:
  400600:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  400604:	f9401611 	ldr	x17, [x16, #40]
  400608:	9100a210 	add	x16, x16, #0x28
  40060c:	d61f0220 	br	x17

0000000000400610 <free@plt>:
  400610:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  400614:	f9401a11 	ldr	x17, [x16, #48]
  400618:	9100c210 	add	x16, x16, #0x30
  40061c:	d61f0220 	br	x17

0000000000400620 <printf@plt>:
  400620:	b0000090 	adrp	x16, 411000 <exit@GLIBC_2.17>
  400624:	f9401e11 	ldr	x17, [x16, #56]
  400628:	9100e210 	add	x16, x16, #0x38
  40062c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400630 <_start>:
  400630:	d280001d 	mov	x29, #0x0                   	// #0
  400634:	d280001e 	mov	x30, #0x0                   	// #0
  400638:	aa0003e5 	mov	x5, x0
  40063c:	f94003e1 	ldr	x1, [sp]
  400640:	910023e2 	add	x2, sp, #0x8
  400644:	910003e6 	mov	x6, sp
  400648:	580000c0 	ldr	x0, 400660 <_start+0x30>
  40064c:	580000e3 	ldr	x3, 400668 <_start+0x38>
  400650:	58000104 	ldr	x4, 400670 <_start+0x40>
  400654:	97ffffdf 	bl	4005d0 <__libc_start_main@plt>
  400658:	97ffffe6 	bl	4005f0 <abort@plt>
  40065c:	00000000 	.inst	0x00000000 ; undefined
  400660:	00400ae8 	.word	0x00400ae8
  400664:	00000000 	.word	0x00000000
  400668:	00400c30 	.word	0x00400c30
  40066c:	00000000 	.word	0x00000000
  400670:	00400cb0 	.word	0x00400cb0
  400674:	00000000 	.word	0x00000000

0000000000400678 <call_weak_fn>:
  400678:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf2b4>
  40067c:	f947f000 	ldr	x0, [x0, #4064]
  400680:	b4000040 	cbz	x0, 400688 <call_weak_fn+0x10>
  400684:	17ffffd7 	b	4005e0 <__gmon_start__@plt>
  400688:	d65f03c0 	ret
  40068c:	00000000 	.inst	0x00000000 ; undefined

0000000000400690 <deregister_tm_clones>:
  400690:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400694:	91014000 	add	x0, x0, #0x50
  400698:	b0000081 	adrp	x1, 411000 <exit@GLIBC_2.17>
  40069c:	91014021 	add	x1, x1, #0x50
  4006a0:	eb00003f 	cmp	x1, x0
  4006a4:	540000a0 	b.eq	4006b8 <deregister_tm_clones+0x28>  // b.none
  4006a8:	90000001 	adrp	x1, 400000 <_init-0x570>
  4006ac:	f9466821 	ldr	x1, [x1, #3280]
  4006b0:	b4000041 	cbz	x1, 4006b8 <deregister_tm_clones+0x28>
  4006b4:	d61f0020 	br	x1
  4006b8:	d65f03c0 	ret
  4006bc:	d503201f 	nop

00000000004006c0 <register_tm_clones>:
  4006c0:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  4006c4:	91014000 	add	x0, x0, #0x50
  4006c8:	b0000081 	adrp	x1, 411000 <exit@GLIBC_2.17>
  4006cc:	91014021 	add	x1, x1, #0x50
  4006d0:	cb000021 	sub	x1, x1, x0
  4006d4:	9343fc21 	asr	x1, x1, #3
  4006d8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4006dc:	9341fc21 	asr	x1, x1, #1
  4006e0:	b40000a1 	cbz	x1, 4006f4 <register_tm_clones+0x34>
  4006e4:	90000002 	adrp	x2, 400000 <_init-0x570>
  4006e8:	f9466c42 	ldr	x2, [x2, #3288]
  4006ec:	b4000042 	cbz	x2, 4006f4 <register_tm_clones+0x34>
  4006f0:	d61f0040 	br	x2
  4006f4:	d65f03c0 	ret

00000000004006f8 <__do_global_dtors_aux>:
  4006f8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006fc:	910003fd 	mov	x29, sp
  400700:	f9000bf3 	str	x19, [sp, #16]
  400704:	b0000093 	adrp	x19, 411000 <exit@GLIBC_2.17>
  400708:	39414260 	ldrb	w0, [x19, #80]
  40070c:	35000080 	cbnz	w0, 40071c <__do_global_dtors_aux+0x24>
  400710:	97ffffe0 	bl	400690 <deregister_tm_clones>
  400714:	52800020 	mov	w0, #0x1                   	// #1
  400718:	39014260 	strb	w0, [x19, #80]
  40071c:	f9400bf3 	ldr	x19, [sp, #16]
  400720:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400724:	d65f03c0 	ret

0000000000400728 <frame_dummy>:
  400728:	17ffffe6 	b	4006c0 <register_tm_clones>

000000000040072c <add>:
  40072c:	d10083ff 	sub	sp, sp, #0x20
  400730:	f90007e0 	str	x0, [sp, #8]
  400734:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400738:	91016000 	add	x0, x0, #0x58
  40073c:	f9400000 	ldr	x0, [x0]
  400740:	f100001f 	cmp	x0, #0x0
  400744:	54000920 	b.eq	400868 <add+0x13c>  // b.none
  400748:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  40074c:	91016000 	add	x0, x0, #0x58
  400750:	f9400000 	ldr	x0, [x0]
  400754:	f9000fe0 	str	x0, [sp, #24]
  400758:	f9400fe0 	ldr	x0, [sp, #24]
  40075c:	f9000be0 	str	x0, [sp, #16]
  400760:	1400002d 	b	400814 <add+0xe8>
  400764:	f9400fe0 	ldr	x0, [sp, #24]
  400768:	b9401001 	ldr	w1, [x0, #16]
  40076c:	f94007e0 	ldr	x0, [sp, #8]
  400770:	b9401000 	ldr	w0, [x0, #16]
  400774:	6b00003f 	cmp	w1, w0
  400778:	540000ec 	b.gt	400794 <add+0x68>
  40077c:	f9400fe0 	ldr	x0, [sp, #24]
  400780:	f9000be0 	str	x0, [sp, #16]
  400784:	f9400fe0 	ldr	x0, [sp, #24]
  400788:	f9400400 	ldr	x0, [x0, #8]
  40078c:	f9000fe0 	str	x0, [sp, #24]
  400790:	1400000e 	b	4007c8 <add+0x9c>
  400794:	f9400be0 	ldr	x0, [sp, #16]
  400798:	f94007e1 	ldr	x1, [sp, #8]
  40079c:	f9000401 	str	x1, [x0, #8]
  4007a0:	f94007e0 	ldr	x0, [sp, #8]
  4007a4:	f9400be1 	ldr	x1, [sp, #16]
  4007a8:	f9000001 	str	x1, [x0]
  4007ac:	f94007e0 	ldr	x0, [sp, #8]
  4007b0:	f9400fe1 	ldr	x1, [sp, #24]
  4007b4:	f9000401 	str	x1, [x0, #8]
  4007b8:	f9400fe0 	ldr	x0, [sp, #24]
  4007bc:	f94007e1 	ldr	x1, [sp, #8]
  4007c0:	f9000001 	str	x1, [x0]
  4007c4:	14000018 	b	400824 <add+0xf8>
  4007c8:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  4007cc:	91016000 	add	x0, x0, #0x58
  4007d0:	f9400000 	ldr	x0, [x0]
  4007d4:	f9400fe1 	ldr	x1, [sp, #24]
  4007d8:	eb00003f 	cmp	x1, x0
  4007dc:	540001c1 	b.ne	400814 <add+0xe8>  // b.any
  4007e0:	f9400be0 	ldr	x0, [sp, #16]
  4007e4:	f94007e1 	ldr	x1, [sp, #8]
  4007e8:	f9000401 	str	x1, [x0, #8]
  4007ec:	f94007e0 	ldr	x0, [sp, #8]
  4007f0:	f9400be1 	ldr	x1, [sp, #16]
  4007f4:	f9000001 	str	x1, [x0]
  4007f8:	f94007e0 	ldr	x0, [sp, #8]
  4007fc:	f9400fe1 	ldr	x1, [sp, #24]
  400800:	f9000401 	str	x1, [x0, #8]
  400804:	f9400fe0 	ldr	x0, [sp, #24]
  400808:	f94007e1 	ldr	x1, [sp, #8]
  40080c:	f9000001 	str	x1, [x0]
  400810:	14000005 	b	400824 <add+0xf8>
  400814:	f9400fe0 	ldr	x0, [sp, #24]
  400818:	f9400400 	ldr	x0, [x0, #8]
  40081c:	f100001f 	cmp	x0, #0x0
  400820:	54fffa21 	b.ne	400764 <add+0x38>  // b.any
  400824:	f9400fe0 	ldr	x0, [sp, #24]
  400828:	f9400400 	ldr	x0, [x0, #8]
  40082c:	f100001f 	cmp	x0, #0x0
  400830:	540001e1 	b.ne	40086c <add+0x140>  // b.any
  400834:	f9400be0 	ldr	x0, [sp, #16]
  400838:	f94007e1 	ldr	x1, [sp, #8]
  40083c:	f9000401 	str	x1, [x0, #8]
  400840:	f94007e0 	ldr	x0, [sp, #8]
  400844:	f9400fe1 	ldr	x1, [sp, #24]
  400848:	f9000401 	str	x1, [x0, #8]
  40084c:	f94007e0 	ldr	x0, [sp, #8]
  400850:	f9400be1 	ldr	x1, [sp, #16]
  400854:	f9000001 	str	x1, [x0]
  400858:	f9400fe0 	ldr	x0, [sp, #24]
  40085c:	f94007e1 	ldr	x1, [sp, #8]
  400860:	f9000001 	str	x1, [x0]
  400864:	14000002 	b	40086c <add+0x140>
  400868:	d503201f 	nop
  40086c:	910083ff 	add	sp, sp, #0x20
  400870:	d65f03c0 	ret

0000000000400874 <del>:
  400874:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400878:	910003fd 	mov	x29, sp
  40087c:	b9001fa0 	str	w0, [x29, #28]
  400880:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400884:	91016000 	add	x0, x0, #0x58
  400888:	f9400000 	ldr	x0, [x0]
  40088c:	f9400400 	ldr	x0, [x0, #8]
  400890:	f9001fa0 	str	x0, [x29, #56]
  400894:	f9401fa0 	ldr	x0, [x29, #56]
  400898:	f9001ba0 	str	x0, [x29, #48]
  40089c:	14000026 	b	400934 <del+0xc0>
  4008a0:	f9401fa0 	ldr	x0, [x29, #56]
  4008a4:	b9401000 	ldr	w0, [x0, #16]
  4008a8:	b9401fa1 	ldr	w1, [x29, #28]
  4008ac:	6b00003f 	cmp	w1, w0
  4008b0:	54000241 	b.ne	4008f8 <del+0x84>  // b.any
  4008b4:	f9401fa0 	ldr	x0, [x29, #56]
  4008b8:	f90017a0 	str	x0, [x29, #40]
  4008bc:	f9401fa0 	ldr	x0, [x29, #56]
  4008c0:	f9400401 	ldr	x1, [x0, #8]
  4008c4:	f9401ba0 	ldr	x0, [x29, #48]
  4008c8:	f9000401 	str	x1, [x0, #8]
  4008cc:	f9401fa0 	ldr	x0, [x29, #56]
  4008d0:	f9400400 	ldr	x0, [x0, #8]
  4008d4:	f9401ba1 	ldr	x1, [x29, #48]
  4008d8:	f9000001 	str	x1, [x0]
  4008dc:	f94017a0 	ldr	x0, [x29, #40]
  4008e0:	97ffff4c 	bl	400610 <free@plt>
  4008e4:	90000000 	adrp	x0, 400000 <_init-0x570>
  4008e8:	91338000 	add	x0, x0, #0xce0
  4008ec:	b9401fa1 	ldr	w1, [x29, #28]
  4008f0:	97ffff4c 	bl	400620 <printf@plt>
  4008f4:	14000018 	b	400954 <del+0xe0>
  4008f8:	f9401fa0 	ldr	x0, [x29, #56]
  4008fc:	b9401000 	ldr	w0, [x0, #16]
  400900:	b9401fa1 	ldr	w1, [x29, #28]
  400904:	6b00003f 	cmp	w1, w0
  400908:	540000ed 	b.le	400924 <del+0xb0>
  40090c:	f9401fa0 	ldr	x0, [x29, #56]
  400910:	f9001ba0 	str	x0, [x29, #48]
  400914:	f9401fa0 	ldr	x0, [x29, #56]
  400918:	f9400400 	ldr	x0, [x0, #8]
  40091c:	f9001fa0 	str	x0, [x29, #56]
  400920:	14000005 	b	400934 <del+0xc0>
  400924:	90000000 	adrp	x0, 400000 <_init-0x570>
  400928:	91340000 	add	x0, x0, #0xd00
  40092c:	97ffff35 	bl	400600 <puts@plt>
  400930:	14000009 	b	400954 <del+0xe0>
  400934:	f9401fa0 	ldr	x0, [x29, #56]
  400938:	f9400401 	ldr	x1, [x0, #8]
  40093c:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400940:	91016000 	add	x0, x0, #0x58
  400944:	f9400000 	ldr	x0, [x0]
  400948:	f9400400 	ldr	x0, [x0, #8]
  40094c:	eb00003f 	cmp	x1, x0
  400950:	54fffa81 	b.ne	4008a0 <del+0x2c>  // b.any
  400954:	d503201f 	nop
  400958:	a8c47bfd 	ldp	x29, x30, [sp], #64
  40095c:	d65f03c0 	ret

0000000000400960 <new>:
  400960:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400964:	910003fd 	mov	x29, sp
  400968:	d2800300 	mov	x0, #0x18                  	// #24
  40096c:	97ffff15 	bl	4005c0 <malloc@plt>
  400970:	f9000fa0 	str	x0, [x29, #24]
  400974:	f9400fa0 	ldr	x0, [x29, #24]
  400978:	f100001f 	cmp	x0, #0x0
  40097c:	540000c1 	b.ne	400994 <new+0x34>  // b.any
  400980:	90000000 	adrp	x0, 400000 <_init-0x570>
  400984:	91342000 	add	x0, x0, #0xd08
  400988:	97ffff1e 	bl	400600 <puts@plt>
  40098c:	d2800000 	mov	x0, #0x0                   	// #0
  400990:	1400000c 	b	4009c0 <new+0x60>
  400994:	f9400fa0 	ldr	x0, [x29, #24]
  400998:	12800001 	mov	w1, #0xffffffff            	// #-1
  40099c:	b9001001 	str	w1, [x0, #16]
  4009a0:	f9400fa0 	ldr	x0, [x29, #24]
  4009a4:	12800001 	mov	w1, #0xffffffff            	// #-1
  4009a8:	b9001401 	str	w1, [x0, #20]
  4009ac:	f9400fa0 	ldr	x0, [x29, #24]
  4009b0:	f900001f 	str	xzr, [x0]
  4009b4:	f9400fa0 	ldr	x0, [x29, #24]
  4009b8:	f900041f 	str	xzr, [x0, #8]
  4009bc:	f9400fa0 	ldr	x0, [x29, #24]
  4009c0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4009c4:	d65f03c0 	ret

00000000004009c8 <display>:
  4009c8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4009cc:	910003fd 	mov	x29, sp
  4009d0:	b9001fa0 	str	w0, [x29, #28]
  4009d4:	52800020 	mov	w0, #0x1                   	// #1
  4009d8:	b90027a0 	str	w0, [x29, #36]
  4009dc:	b9401fa0 	ldr	w0, [x29, #28]
  4009e0:	7100001f 	cmp	w0, #0x0
  4009e4:	54000401 	b.ne	400a64 <display+0x9c>  // b.any
  4009e8:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  4009ec:	91016000 	add	x0, x0, #0x58
  4009f0:	f9400000 	ldr	x0, [x0]
  4009f4:	f9400400 	ldr	x0, [x0, #8]
  4009f8:	f90017a0 	str	x0, [x29, #40]
  4009fc:	90000000 	adrp	x0, 400000 <_init-0x570>
  400a00:	91348000 	add	x0, x0, #0xd20
  400a04:	97fffeff 	bl	400600 <puts@plt>
  400a08:	1400000e 	b	400a40 <display+0x78>
  400a0c:	b94027a0 	ldr	w0, [x29, #36]
  400a10:	11000401 	add	w1, w0, #0x1
  400a14:	b90027a1 	str	w1, [x29, #36]
  400a18:	f94017a1 	ldr	x1, [x29, #40]
  400a1c:	b9401022 	ldr	w2, [x1, #16]
  400a20:	90000001 	adrp	x1, 400000 <_init-0x570>
  400a24:	9134c023 	add	x3, x1, #0xd30
  400a28:	2a0003e1 	mov	w1, w0
  400a2c:	aa0303e0 	mov	x0, x3
  400a30:	97fffefc 	bl	400620 <printf@plt>
  400a34:	f94017a0 	ldr	x0, [x29, #40]
  400a38:	f9400400 	ldr	x0, [x0, #8]
  400a3c:	f90017a0 	str	x0, [x29, #40]
  400a40:	f94017a0 	ldr	x0, [x29, #40]
  400a44:	f9400401 	ldr	x1, [x0, #8]
  400a48:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400a4c:	91016000 	add	x0, x0, #0x58
  400a50:	f9400000 	ldr	x0, [x0]
  400a54:	f9400400 	ldr	x0, [x0, #8]
  400a58:	eb00003f 	cmp	x1, x0
  400a5c:	54fffd81 	b.ne	400a0c <display+0x44>  // b.any
  400a60:	1400001f 	b	400adc <display+0x114>
  400a64:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400a68:	91016000 	add	x0, x0, #0x58
  400a6c:	f9400000 	ldr	x0, [x0]
  400a70:	f9400000 	ldr	x0, [x0]
  400a74:	f90017a0 	str	x0, [x29, #40]
  400a78:	90000000 	adrp	x0, 400000 <_init-0x570>
  400a7c:	91350000 	add	x0, x0, #0xd40
  400a80:	97fffee0 	bl	400600 <puts@plt>
  400a84:	1400000e 	b	400abc <display+0xf4>
  400a88:	b94027a0 	ldr	w0, [x29, #36]
  400a8c:	11000401 	add	w1, w0, #0x1
  400a90:	b90027a1 	str	w1, [x29, #36]
  400a94:	f94017a1 	ldr	x1, [x29, #40]
  400a98:	b9401022 	ldr	w2, [x1, #16]
  400a9c:	90000001 	adrp	x1, 400000 <_init-0x570>
  400aa0:	9134c023 	add	x3, x1, #0xd30
  400aa4:	2a0003e1 	mov	w1, w0
  400aa8:	aa0303e0 	mov	x0, x3
  400aac:	97fffedd 	bl	400620 <printf@plt>
  400ab0:	f94017a0 	ldr	x0, [x29, #40]
  400ab4:	f9400000 	ldr	x0, [x0]
  400ab8:	f90017a0 	str	x0, [x29, #40]
  400abc:	f94017a0 	ldr	x0, [x29, #40]
  400ac0:	f9400001 	ldr	x1, [x0]
  400ac4:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400ac8:	91016000 	add	x0, x0, #0x58
  400acc:	f9400000 	ldr	x0, [x0]
  400ad0:	f9400000 	ldr	x0, [x0]
  400ad4:	eb00003f 	cmp	x1, x0
  400ad8:	54fffd81 	b.ne	400a88 <display+0xc0>  // b.any
  400adc:	d503201f 	nop
  400ae0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400ae4:	d65f03c0 	ret

0000000000400ae8 <main>:
  400ae8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400aec:	910003fd 	mov	x29, sp
  400af0:	97ffff9c 	bl	400960 <new>
  400af4:	aa0003e1 	mov	x1, x0
  400af8:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400afc:	91016000 	add	x0, x0, #0x58
  400b00:	f9000001 	str	x1, [x0]
  400b04:	b0000080 	adrp	x0, 411000 <exit@GLIBC_2.17>
  400b08:	91016000 	add	x0, x0, #0x58
  400b0c:	f9400000 	ldr	x0, [x0]
  400b10:	f100001f 	cmp	x0, #0x0
  400b14:	54000061 	b.ne	400b20 <main+0x38>  // b.any
  400b18:	12800000 	mov	w0, #0xffffffff            	// #-1
  400b1c:	97fffea5 	bl	4005b0 <exit@plt>
  400b20:	b9001fbf 	str	wzr, [x29, #28]
  400b24:	1400000f 	b	400b60 <main+0x78>
  400b28:	97ffff8e 	bl	400960 <new>
  400b2c:	f9000ba0 	str	x0, [x29, #16]
  400b30:	f9400ba0 	ldr	x0, [x29, #16]
  400b34:	b9401fa1 	ldr	w1, [x29, #28]
  400b38:	b9001001 	str	w1, [x0, #16]
  400b3c:	b9401fa0 	ldr	w0, [x29, #28]
  400b40:	11000401 	add	w1, w0, #0x1
  400b44:	f9400ba0 	ldr	x0, [x29, #16]
  400b48:	b9001401 	str	w1, [x0, #20]
  400b4c:	f9400ba0 	ldr	x0, [x29, #16]
  400b50:	97fffef7 	bl	40072c <add>
  400b54:	b9401fa0 	ldr	w0, [x29, #28]
  400b58:	11000400 	add	w0, w0, #0x1
  400b5c:	b9001fa0 	str	w0, [x29, #28]
  400b60:	b9401fa0 	ldr	w0, [x29, #28]
  400b64:	7100241f 	cmp	w0, #0x9
  400b68:	54fffe0d 	b.le	400b28 <main+0x40>
  400b6c:	52800000 	mov	w0, #0x0                   	// #0
  400b70:	97ffff96 	bl	4009c8 <display>
  400b74:	52800040 	mov	w0, #0x2                   	// #2
  400b78:	97ffff3f 	bl	400874 <del>
  400b7c:	52800060 	mov	w0, #0x3                   	// #3
  400b80:	97ffff3d 	bl	400874 <del>
  400b84:	528000c0 	mov	w0, #0x6                   	// #6
  400b88:	97ffff3b 	bl	400874 <del>
  400b8c:	52800000 	mov	w0, #0x0                   	// #0
  400b90:	97ffff8e 	bl	4009c8 <display>
  400b94:	97ffff73 	bl	400960 <new>
  400b98:	f9000ba0 	str	x0, [x29, #16]
  400b9c:	f9400ba0 	ldr	x0, [x29, #16]
  400ba0:	52800b01 	mov	w1, #0x58                  	// #88
  400ba4:	b9001001 	str	w1, [x0, #16]
  400ba8:	f9400ba0 	ldr	x0, [x29, #16]
  400bac:	52800b01 	mov	w1, #0x58                  	// #88
  400bb0:	b9001401 	str	w1, [x0, #20]
  400bb4:	f9400ba0 	ldr	x0, [x29, #16]
  400bb8:	97fffedd 	bl	40072c <add>
  400bbc:	52800000 	mov	w0, #0x0                   	// #0
  400bc0:	97ffff82 	bl	4009c8 <display>
  400bc4:	97ffff67 	bl	400960 <new>
  400bc8:	f9000ba0 	str	x0, [x29, #16]
  400bcc:	f9400ba0 	ldr	x0, [x29, #16]
  400bd0:	528009a1 	mov	w1, #0x4d                  	// #77
  400bd4:	b9001001 	str	w1, [x0, #16]
  400bd8:	f9400ba0 	ldr	x0, [x29, #16]
  400bdc:	528009a1 	mov	w1, #0x4d                  	// #77
  400be0:	b9001401 	str	w1, [x0, #20]
  400be4:	f9400ba0 	ldr	x0, [x29, #16]
  400be8:	97fffed1 	bl	40072c <add>
  400bec:	52800000 	mov	w0, #0x0                   	// #0
  400bf0:	97ffff76 	bl	4009c8 <display>
  400bf4:	97ffff5b 	bl	400960 <new>
  400bf8:	f9000ba0 	str	x0, [x29, #16]
  400bfc:	f9400ba0 	ldr	x0, [x29, #16]
  400c00:	52800841 	mov	w1, #0x42                  	// #66
  400c04:	b9001001 	str	w1, [x0, #16]
  400c08:	f9400ba0 	ldr	x0, [x29, #16]
  400c0c:	52800841 	mov	w1, #0x42                  	// #66
  400c10:	b9001401 	str	w1, [x0, #20]
  400c14:	f9400ba0 	ldr	x0, [x29, #16]
  400c18:	97fffec5 	bl	40072c <add>
  400c1c:	52800000 	mov	w0, #0x0                   	// #0
  400c20:	97ffff6a 	bl	4009c8 <display>
  400c24:	52800000 	mov	w0, #0x0                   	// #0
  400c28:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400c2c:	d65f03c0 	ret

0000000000400c30 <__libc_csu_init>:
  400c30:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400c34:	910003fd 	mov	x29, sp
  400c38:	a901d7f4 	stp	x20, x21, [sp, #24]
  400c3c:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf2b4>
  400c40:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf2b4>
  400c44:	91374294 	add	x20, x20, #0xdd0
  400c48:	913722b5 	add	x21, x21, #0xdc8
  400c4c:	a902dff6 	stp	x22, x23, [sp, #40]
  400c50:	cb150294 	sub	x20, x20, x21
  400c54:	f9001ff8 	str	x24, [sp, #56]
  400c58:	2a0003f6 	mov	w22, w0
  400c5c:	aa0103f7 	mov	x23, x1
  400c60:	9343fe94 	asr	x20, x20, #3
  400c64:	aa0203f8 	mov	x24, x2
  400c68:	97fffe42 	bl	400570 <_init>
  400c6c:	b4000194 	cbz	x20, 400c9c <__libc_csu_init+0x6c>
  400c70:	f9000bb3 	str	x19, [x29, #16]
  400c74:	d2800013 	mov	x19, #0x0                   	// #0
  400c78:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400c7c:	aa1803e2 	mov	x2, x24
  400c80:	aa1703e1 	mov	x1, x23
  400c84:	2a1603e0 	mov	w0, w22
  400c88:	91000673 	add	x19, x19, #0x1
  400c8c:	d63f0060 	blr	x3
  400c90:	eb13029f 	cmp	x20, x19
  400c94:	54ffff21 	b.ne	400c78 <__libc_csu_init+0x48>  // b.any
  400c98:	f9400bb3 	ldr	x19, [x29, #16]
  400c9c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400ca0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400ca4:	f9401ff8 	ldr	x24, [sp, #56]
  400ca8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400cac:	d65f03c0 	ret

0000000000400cb0 <__libc_csu_fini>:
  400cb0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400cb4 <_fini>:
  400cb4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400cb8:	910003fd 	mov	x29, sp
  400cbc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400cc0:	d65f03c0 	ret
